
module top_add_tc_16_16(
    input               clk,
    input               rst_n,
    input       [15:0]  a,
    input       [15:0]  b,
    output  reg [16:0]  sum
);
    reg   [15:0]    a_r;
    reg   [15:0]    b_r;
    wire  [16:0]    sum_r;

    add_tc_16_16 inst_add_tc_16_16 (.a(a_r), .b(b_r), .sum(sum_r));


always @(posedge clk ) begin
    if (!rst_n) begin
        sum     <=    16'b0;
        a_r     <=    16'b0;
        b_r     <=    16'b0;
    end
    else begin
        sum     <=      sum_r;
        a_r     <=      a;
        b_r     <=      b;
    end
end     

endmodule